Kodingan VHDL D Flip Flop

VHDL Code For D-FF Structural Model

VHDL Code For D-FF Structural Model

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dffst is

Port ( d,clk : in  STD_LOGIC;

q,qb : inout STD_LOGIC);

end dffst;

architecture dffstar of dffst is

component nand21

port(a,b: in STD_LOGIC;

y:out STD_LOGIC);

end component;

signal d1,s1,r1:STD_LOGIC;

begin

n0: nand21 port map(d,clk,s1);

n1: nand21 port map(d,d,d1);

n2: nand21 port map(d1,clk,r1);

n3: nand21 port map(s1,qb,q);

n4: nand21 port map(r1,q,qb);

end dffstar;

– nand gate

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity nand21 is

Port ( a,b : in  STD_LOGIC;

y : out  STD_LOGIC);

end nand21;

architecture Behavioral of nand21 is

begin

y <= a nand b;

end Behavioral;

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VHDL Code For D-FF Behavioral Model

VHDL Code For D-FF Behavioral Model

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dffbeh is

Port ( d,clk : in  STD_LOGIC;

q,qb : inout STD_LOGIC);

end dffbeh;

architecture dffbehar of dffbeh is

begin

process(d,clk)

begin

if(clk’event and clk=’1′) then q<=d; qb<=not d;

end if;

end process;

end dffbehar;

VHDL Code For D-FF Data Flow Model

VHDL Code For D-FF Data Flow Model

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dffdf is

Port ( d,clk : in  STD_LOGIC;

q,qb : inout STD_LOGIC);

end dffdf;

architecture dffdfar of dffdf is

signal d1,s1,r1:STD_LOGIC;

begin

s1 <= d nand clk;

d1 <= d nand d;

r1 <= d1 nand clk;

q <= s1 nand qb;

qb <= r1 nand q;

end dffdfar;